1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to a novel replacement gate process flow that may be employed in manufacturing highly scaled semiconductor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Field effect transistors (NFET and PFET transistors) represent one important type of circuit element that substantially determines performance of the integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NFET transistors and/or PFET transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NFET transistor or a PFET transistor is considered, typically comprises doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin gate insulation layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends upon, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as the channel length of the transistor. Thus, in modern ultra-high density integrated circuits, device features, like the channel length, have been steadily decreasing in size to enhance the performance of the semiconductor device and the overall functionality of the circuit.
However, the ongoing shrinkage of feature sizes on transistor devices causes certain problems that may at least partially offset the advantages that may be obtained by reduction of the device features. Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 30-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use of metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NFET transistors and create a compressive stress in the channel region for PFET transistors). Stress engineering techniques typically involve the formation of specifically made silicon nitride layers that are selectively formed above appropriate transistors, i.e., a layer of silicon nitride that is intended to impart a tensile stress in the channel region of an NFET transistor would only be formed above the NFET transistors. Such selective formation may be accomplished by masking the PFET transistors and then blanket depositing the layer of silicon nitride, or by initially blanket depositing the layer of silicon nitride across the entire substrate and then performing an etching process to selectively remove the silicon nitride from above the PFET transistors. Conversely, for PFET transistors, a layer of silicon nitride that is intended to impart a compressive stress in the channel region of a PFET transistor is formed above the PFET transistors. The techniques employed in forming such nitride layers with the desired tensile or compressive stress are well known to those skilled in the art.
For many early device technology generations, the gate electrode structures of most transistor elements has comprised a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly smaller, many newer generation devices employ gate electrode stacks comprising alternative materials in an effort to avoid the short-channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 14-32 nm, gate electrode stacks comprising a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the heretofore more commonly used silicon dioxide/polysilicon (SiO/poly) configurations.
One well-known processing method that has been used for forming a transistor with a high-k/metal gate structure is the so-called “gate last” or “replacement gate” technique. FIGS. 1A-1H depict one illustrative prior art process flow for forming a semiconductor device 100 that includes an illustrative PFET transistor 100P and an illustrative NFET transistor 100N using a replacement gate technique. FIG. 1A schematically depicts the device 100 after several process operations have been performed. Initially, illustrative shallow trench isolation structures 12 are formed in the substrate 10. Thereafter, “dummy” gate structures 14 will be formed for the PFET transistor 100P and the NFET transistor 100N in and above regions of the substrate 10 that are separated by the illustrative shallow trench isolation structure 12. The dummy gate structures 14 generally include a gate insulation layer 14A and a gate electrode layer 14B. A gate cap layer 16, made of a material such as silicon nitride, is formed above the gate structures 14. The gate insulation layer 14A may be comprised of a variety of materials, such as silicon dioxide. The gate electrode layer 14B may be comprised of one or more layers of conductive materials, such as polysilicon, etc. The structure depicted in FIG. 1A may be formed by performing a variety of known techniques. For example, the layers of material that make up the gate insulation layer 14A, the gate electrode layer 14B and the gate cap layer 16 may be blanket deposited above the substrate 10 and, thereafter, one or more etching processes are performed through a patterned mask layer (not shown) to define the dummy gate structures 14 depicted in FIG. 1A. At this point, if desired, one or more implantation processes may be performed to form extension implant regions and/or so-called halo implant regions for one or both of the PFET transistor 100P and the NFET transistor 100N by performing known ion implantation and masking operations. However, such implant regions are not depicted in the attached drawings. With continuing reference to FIG. 1A, illustrative silicon nitride sidewall spacers 20 with an illustrative base width of about 5-10 nm are formed adjacent dummy gate structures 14 for both the PFET transistor 100P and the NFET transistor 100N. The spacers 20 may be formed by depositing a layer of spacer material and thereafter performing an anisotropic etching process. One or more of the various ion implant processes mentioned above may be formed after the formation of the spacers 20.
FIG. 1B depicts the device 100 after several process operations have been performed. More specifically, a hard mask layer 22, made of a material such as silicon nitride, is formed above the NFET transistor 100N. The hard mask layer 22 may be formed by blanket depositing the hard mask layer 22 across the device 100 and, thereafter, forming a masking layer (not shown), e.g., such as a photoresist mask, so as to cover the NFET transistor 100N and expose the PFET transistor 100P for further processing. Then, an etching process is performed to remove the hard mask layer 22 from above the PFET transistor 100P. Next, one or more etching processes are performed to define cavities 24 in areas of the substrate 10 where source/drain regions for the PFET transistor 100P will ultimately be formed. In some cases, the spacers 20 may be removed prior to the formation of the cavities 24. The depth and shape of the cavities 24 may vary depending upon the particular application. In one example, where the cavities 24 have an overall depth 25 of about 70 nm, the cavities 24 may be formed by performing an initial dry anisotropic etching process to a depth of about 40-50 nm and, thereafter, performing a wet etching process using, for example, TMAH, which has an etch rate that varies based upon the crystalline structure of the substrate 10, e.g., the etching process using TMAH exhibits a higher etch rate in the <110> direction than it does in the <100> direction.
FIG. 1C depicts the device 100 after an epitaxial deposition process is performed to form epitaxial silicon/germanium regions 26 in the cavities 24. In the depicted example, the regions 26 have an overfill portion that extends above the surface of the substrate 10 by, for example, a distance of about 25 nm. The epitaxial silicon/germanium regions 26 may be formed by performing well-known epitaxial deposition processes, and a P-type dopant material may be introduced into the epitaxial silicon/germanium regions 26 as they are being formed, i.e., an in situ doping process.
As shown in FIG. 1D, after the epitaxial silicon/germanium regions 26 are formed, the PFET transistor 100P may be covered by a photoresist mask (not shown) and an etching process using, for example, hot phosphoric acid, may be performed to remove the hard mask layer 22 from above the NFET transistor 100N. At this point, a source/drain ion implant process using an N-type dopant may be performed to form source/drain regions (not shown) on the NFET transistor 100N. Then, a layer of insulating material 30 such as, for example, silicon dioxide, is blanket deposited across the device 100.
Next, as shown in FIG. 1E, one or more chemical mechanical polishing (CMP) processes have been performed to remove any materials above the sacrificial gate electrode 14B so that the sacrificial gate structure 14 may be removed.
Then, as shown in FIG. 1F, one or more etching processes are performed to remove the sacrificial gate electrode 14B and the sacrificial gate insulation layer 14A to thereby define a gate cavity 32 where a replacement gate structure will subsequently be formed. A masking layer that is typically used in such etching processes is not depicted for purposes of clarity. Typically, the sacrificial gate insulation layer 14A is removed as part of the replacement gate technique, as depicted herein. However, the sacrificial gate insulation layer 14A may not be removed in all applications.
Next, as shown in FIG. 1G, various layers of material that will constitute a replacement gate structure 40P for the PFET transistor 100P and a replacement gate structure 40N for the NFET transistor are formed in the gate cavities 32 (FIG. 1F). Typically, the gate insulation layer 40A for the replacement gate structures for both the PFET and NFET transistors will be the same, e.g., a high-k (k value greater than about 10) gate insulation layer 40A, such as hafnium oxide, having a thickness of approximately 2 nm. The gate electrodes 40BP, 40BN of the replacement gate structures 40P, 40N, respectively, will typically be comprised of multiple layers of conductive material, e.g., one or more metal layers, and the number of materials and the type of materials used for the gate electrode 40BP in the replacement gate structure 40P for the PFET transistor 100P may be different than the materials used for the gate electrode 40BN in the replacement gate structure 40N for the NFET transistor 100N. In some cases, the use of additional materials for the gate electrode 40BP for the PFET transistor 100P results in the PFET transistor 100P having a taller gate structure than that of the NFET transistor 100N. However, such a height differential is not depicted in the attached drawings. The materials that are used to form the gate structures 40P, 40N are typically conformably deposited in the gate cavities 32 and above the layer of insulating material 30. To the extent that different materials are used on the different devices 100P, 100N, appropriate masking layers (not shown) may be formed to allow for the formation of the desired materials on the appropriate device. Ultimately, after all of the materials are formed for the replacement gate structures 40P, 40N, one or more CMP processes are performed to remove excess portions of the material of the gate insulation layer 40A and the various conductive materials that make up the gate electrodes 40BP, 40BN of the gate structures 40P, 40N, respectively, that are positioned outside of the gate cavity to define the replacement gate structures 40P, 40N. Although not depicted in the drawings, at this point in the fabrication process, if desired, stress-inducing material layers (compressive for the PFET transistor 100P and tensile for the NFET transistor 100N) may be formed on the various devices to increase the electrical performance characteristics of the transistors.
Next, as shown in FIG. 1H, a protective cap layer 42, e.g., a layer of silicon nitride, is formed so as to protect the replacement gate structures 40P, 40N, and a layer of insulating material 43, e.g., silicon dioxide, is formed above the protective cap layer 42. Thereafter, using traditional processing techniques, contact openings are formed through the layers of insulating material 30, 43 and the protective cap layer 42 to expose the underlying source/drain regions of the transistor devices 100P, 100N. Metal silicide regions (not shown) are then formed on the exposed portions of the source/drain regions. Thereafter, conductive source drain contacts 44 and conductive gate contacts 46, e.g., titanium nitride contacts, are formed in the openings in the layers of insulating material 30, 43 and the protective cap layer 42 using traditional contact formation techniques and materials. Ultimately, several metallization layers (not shown) will be formed above the device 100 to complete its fabrication.
The present disclosure is directed to a novel replacement gate process flow that may be employed in manufacturing highly scaled semiconductor devices.